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Digital Electronics

GATE-2013

Q:   For 8085 microprocessor, the following program is executed. MVI A, 05H; MVI B, 05H; PTR: ADD B; DCR B; JNZ PTR; ADI 03H; HLT; At the end of program, accumulator contains

  • A:  17H
  • B:  20H
  • C:  23H
  • D:  05H
GATE-2013

Q:   The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is

  • A:  4
  • B:  6
  • C:  8
  • D:  10
GATE-2009

Q:   The full form of the abbreviations TTL and CMOS in reference to logic families are

  • A:  Triple Transistor Logic and Chip Metal Oxide Semiconductor
  • B:  Tristate Transistor Logic and Chip Metal Oxide Semiconductor
  • C:  Transistor Transistor Logic and Complementary Metal Oxide Semiconductor
  • D:  Tristate Transistor Logic and Complementary Metal Oxide Silicon
GATE-2009

Q:   In a microprocessor, the service routine for a certain interrupt starts from a fixed location of memory which cannot be externally set, but the interrupt can be delayed or rejected Such an interrupt is

  • A:  non-maskable and non-vectored
  • B:  maskable and non-vectored
  • C:  non-maskable and vectored
  • D:  maskable and vectored
GATE-2013

Q:   A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be turned ON and also can be turned OFF by any one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles

  • A:  AND
  • B:  OR
  • C:  XOR
  • D:  NAND
GATE-2009

Q:   What are the minimum number of 2- to -1 multiplexers required to generate a 2- input AND gate and a 2- input Ex-OR gate

  • A:  1 and 2
  • B:  1 and 3
  • C:  1 and 1
  • D:  2 and 2
GATE-2008

Q:   The two numbers represented in signed 2’s complement form are P + 11101101 and Q = 11100110. If Q is subtracted from P, the value obtained in signed 2’s complement is

  • A:  1000001111
  • B:  00000111
  • C:  11111001
  • D:  111111001
GATE-2003

Q:   A 4 bit ripple counter and a bit synchronous counter are made using flip flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then

  • A:  R = 10 ns, S = 40 ns
  • B:  R = 40 ns, S = 10 ns
  • C:  R = 10 ns, S = 30 ns
  • D:  R = 30 ns, S = 10 ns
GATE-2003

Q:   In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulator is less than that of register B. As a result

  • A:  Carry flag will be set but Zero flag will be reset
  • B:  Carry flag will be rest but Zero flag will be set
  • C:  Both Carry flag and Zero flag will be rest
  • D:  Both Carry flag and Zero flag will be set
GATE-1996

Q:   A dynamic RAM cell which hold 5 V has to be refreshed every 20 m sec, so that the stored voltage does not fall by more than 0.5 V. If the cell has a constant discharge current of 1 pA, the storage capacitance of the cell is

  • A:  4x10-6 F
  • B:  4x10-9 F
  • C:  4x10-12 F
  • D:  4x10-15 F
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